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Download Symbolic Simulation Methods for Industrial Formal by Robert B. Jones PDF

By Robert B. Jones

Symbolic Simulation tools for commercial Formal Verification comprises certain, yet comparable, techniques to the verification challenge. either are according to symbolic simulation. the 1st process is utilized on the gate point and has been winning in verifying sub-circuits of business microprocessors with tens or even millions of gates. the second one technique is utilized at a high-level of abstraction and is used for high-level descriptions of designs.

The ebook includes 3 major topics:

  • Self consistency, a strategy for deriving a proper specification of layout habit from the layout itself;
  • The use of the parametric representation to encode predicates as sensible vectors for symbolic simulation, an incredible step in addressing the state-explosion challenge;
  • Incremental flushing, a mode used to make sure high-level descriptions of out-of-order execution.
Symbolic Simulation equipment for commercial Formal Verification concludes with paintings on verification of simplified versions of out-of-order processors.

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Extra resources for Symbolic Simulation Methods for Industrial Formal Verification

Sample text

Pipeline hazards are situations which prevent an instruction from moving into the next stage during the next clock cycle. This discussion about hazards is derived from the presentation in [HP90]. Hazards can be grouped into three types: • Structural hazards occur when different instructions compete for the same hardware resources. An example is two instructions trying to write to a single-ported register file simultaneously. • Data hazards occur when one instruction depends on the result of an earlier instruction that is still in the pipeline.

It is also often the case that for certain inputs there are many stateholding elements whose values will not affect any of the state-holding elements that are part of the state relation. This fact can be used to reduce the number of symbolic variables needed even further. Finally, for many circuits, restricting the states and inputs to only reachable and valid combinations reduces the number of variables and the run-time and memory requirements for the verification. The most important factor for using self consistency is to find problems that are a good match with symbolic simulation.

Unlike the verification of the ROB described in the previous section, the verification of the derived reference specification for length decoder was complete.

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