By Santanu Kundu, Santanu Chattopadhyay
Addresses the demanding situations linked to System-on-Chip Integration
Network-on-Chip: the subsequent new release of System-on-Chip Integration
examines the present concerns limiting chip-on-chip conversation potency, and explores Network-on-chip (NoC), a promising substitute that equips designers with the aptitude to provide a scalable, reusable, and high-performance verbal exchange spine via bearing in mind the combination of a big variety of cores on a unmarried system-on-chip (SoC). This publication presents a easy evaluate of themes linked to NoC-based layout: verbal exchange infrastructure layout, communique technique, overview framework, and mapping of purposes onto NoC. It information the layout and review of other proposed NoC buildings, low-power concepts, sign integrity and reliability concerns, program mapping, checking out, and destiny trends.
Utilizing examples of chips which were carried out in and academia, this article offers the complete architectural layout of elements confirmed via implementation in commercial CAD instruments. It describes NoC study and advancements, contains theoretical proofs strengthening the research systems, and contains algorithms utilized in NoC layout and synthesis. furthermore, it considers different upcoming NoC concerns, similar to low-power NoC layout, sign integrity concerns, NoC trying out, reconfiguration, synthesis, and 3D NoC layout.
This textual content contains 12 chapters and covers:
- The evolution of NoC from SoC—its study and developmental challenges
- NoC protocols, elaborating stream keep watch over, on hand community topologies, routing mechanisms, fault tolerance, quality-of-service help, and the layout of community interfaces
- The router layout techniques in NoCs
- The evaluate mechanism of NoC architectures
- The program mapping concepts in NoCs
- Low-power layout strategies particularly in NoCs
- The sign integrity and reliability problems with NoC
- The info of NoC checking out suggestions stated so far
- The challenge of synthesizing application-specific NoCs
- Reconfigurable NoC layout issues
- Direction of destiny examine and improvement within the box of NoC
Network-on-Chip: the following iteration of System-on-Chip Integration
covers the fundamental issues, expertise, and destiny tendencies appropriate to NoC-based layout, and will be utilized by engineers, scholars, and researchers and different execs drawn to computing device structure, embedded platforms, and parallel/distributed systems.